This invention relates to VLSI semiconductor circuits and to controlling signal quality on high speed transmission lines. More particularly it relates to interconnect circuitry for programmable and configurable logic arrays.
FIG. 1 depicts part of a prior art routing resource of a programmable logic device having programmable switches S1-S8 for programmably connecting transmission lines Y1-Y10 to lines LL1, LL2, XIN and XOUT. Switches S1-S8 typically comprise transistors in which the control terminal is controlled by a means not shown to either connect or not connect the lines which intersect at the switch location.
Examples of prior art switching devices are shown in FIG. 2. Switch S1 of FIG. 1 could represent FIG. 2a, in which lead A of FIG. 2a is connected to line XIN of FIG. 1 and lead B is connected to line Y1 of FIG. 1. If a "1" is present in memory cell M1a of FIG. 2a, a high voltage turns on N-channel pass transistor 2a of FIG. 2a, which is represented by switch S1 of FIG. 1, thereby connecting lines XIN and Y1. In the circuit of FIG. 2a, a high signal at lead A produces a signal at lead B lower by one threshold voltage drop than the voltage provided by the control lead from memory cell M1a. In another prior art embodiment, as shown in FIG. 2b, switch S1 of FIG. 1 may comprise a parallel pair of N and P-channel pass transistors 2b1 and 2b2 respectively, controlled by memory cell M1b with complementary output signals Q and Q. As discussed in this application, all memory cells will be assumed to provide two complementary output signals Q and Q. The embodiment of FIG. 2b is preferred for avoiding a threshold voltage drop between points A and B at any voltage when transistors 2b1 and 2b2 are turned on by memory cell Mlb. FIG. 2c shows a third embodiment having a P-channel pass transistor 2c controlled by the inverted signal from memory cell M1c. If a "1" is present in memory cell Mlc of FIG. 2c, a low voltage turns on P-channel transistor 2c of FIG. 2c. This embodiment has the drawback that a low signal at lead A produces a signal at lead B higher by one threshold voltage than the voltage provided by the control lead from memory cell M1c.
Likewise, switch S4 of FIG. 1 could represent FIG. 2a, 2b, or 2c, in which lead A of FIG. 2a, 2b, or 2c is connected to line Y3 of FIG. 1 and lead B of FIG. 2a, 2b, or 2c is connected to line LL2. Other switches S1 through S8 can represent pass transistors shown in FIGS. 2a, 2b or 2c, as desired. If a user of the device shown in FIG. 1 wishes to provide a signal present on input lead IN to output lead OUT, the interconnect device is programmed so that switches S2, S4, S6, and S8 are closed, thereby connecting lines XIN to Y3, Y3 to LL2, LL2 to Y8 and Y8 to XOUT respectively.
An actual device may incorporate enough such programmable interconnect switches in series between an input and an output lead that there is significant attenuation of the signal before it reaches its destination. The attenuation is caused by series resistance and capacitance introduced by the transistor channels and connecting lines. This degradation appears in the form f both slower response (rise time) due to the line and channel capacitances, and altered voltage on the signal line. FIG. 2 shows FET devices, however the equivalent problem would exist with bipolar transistors.
The problem of capacitance is particularly noticeable and serious when a transmission line such as line LL2 serves as a long bus for connecting many circuit elements. In the example of FIG. 1, a high quality signal provided by buffer BIN may not be degraded significantly by passing through switch S2 or by traveling on line Y3 if line Y3 is short and serves few circuit elements, and thus has low capacitance. In the case where line LL2 is long and serves as a bus for connecting many circuit elements, the signal which propagates onto line LL2 may experience RC delay due to the resistance of multiple transistor channels plus the large capacitance of line LL2, so that as it continues to propagate through switch S6, line Y8, switch S8, and line XOUT to buffer BOUT, the propagation delay and slower switching time are unacceptable.